
zifu:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400480 <_init>:
  400480:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400484:	910003fd 	mov	x29, sp
  400488:	94000030 	bl	400548 <call_weak_fn>
  40048c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400490:	d65f03c0 	ret

Disassembly of section .plt:

00000000004004a0 <.plt>:
  4004a0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4004a4:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf5c0>
  4004a8:	f947fe11 	ldr	x17, [x16, #4088]
  4004ac:	913fe210 	add	x16, x16, #0xff8
  4004b0:	d61f0220 	br	x17
  4004b4:	d503201f 	nop
  4004b8:	d503201f 	nop
  4004bc:	d503201f 	nop

00000000004004c0 <__libc_start_main@plt>:
  4004c0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004c4:	f9400211 	ldr	x17, [x16]
  4004c8:	91000210 	add	x16, x16, #0x0
  4004cc:	d61f0220 	br	x17

00000000004004d0 <__gmon_start__@plt>:
  4004d0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004d4:	f9400611 	ldr	x17, [x16, #8]
  4004d8:	91002210 	add	x16, x16, #0x8
  4004dc:	d61f0220 	br	x17

00000000004004e0 <abort@plt>:
  4004e0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004e4:	f9400a11 	ldr	x17, [x16, #16]
  4004e8:	91004210 	add	x16, x16, #0x10
  4004ec:	d61f0220 	br	x17

00000000004004f0 <printf@plt>:
  4004f0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4004f4:	f9400e11 	ldr	x17, [x16, #24]
  4004f8:	91006210 	add	x16, x16, #0x18
  4004fc:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400500 <_start>:
  400500:	d280001d 	mov	x29, #0x0                   	// #0
  400504:	d280001e 	mov	x30, #0x0                   	// #0
  400508:	aa0003e5 	mov	x5, x0
  40050c:	f94003e1 	ldr	x1, [sp]
  400510:	910023e2 	add	x2, sp, #0x8
  400514:	910003e6 	mov	x6, sp
  400518:	580000c0 	ldr	x0, 400530 <_start+0x30>
  40051c:	580000e3 	ldr	x3, 400538 <_start+0x38>
  400520:	58000104 	ldr	x4, 400540 <_start+0x40>
  400524:	97ffffe7 	bl	4004c0 <__libc_start_main@plt>
  400528:	97ffffee 	bl	4004e0 <abort@plt>
  40052c:	00000000 	.inst	0x00000000 ; undefined
  400530:	004008d0 	.word	0x004008d0
  400534:	00000000 	.word	0x00000000
  400538:	00400940 	.word	0x00400940
  40053c:	00000000 	.word	0x00000000
  400540:	004009c0 	.word	0x004009c0
  400544:	00000000 	.word	0x00000000

0000000000400548 <call_weak_fn>:
  400548:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf5c0>
  40054c:	f947f000 	ldr	x0, [x0, #4064]
  400550:	b4000040 	cbz	x0, 400558 <call_weak_fn+0x10>
  400554:	17ffffdf 	b	4004d0 <__gmon_start__@plt>
  400558:	d65f03c0 	ret
  40055c:	00000000 	.inst	0x00000000 ; undefined

0000000000400560 <deregister_tm_clones>:
  400560:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400564:	9100c000 	add	x0, x0, #0x30
  400568:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40056c:	9100c021 	add	x1, x1, #0x30
  400570:	eb00003f 	cmp	x1, x0
  400574:	540000a0 	b.eq	400588 <deregister_tm_clones+0x28>  // b.none
  400578:	90000001 	adrp	x1, 400000 <_init-0x480>
  40057c:	f944f021 	ldr	x1, [x1, #2528]
  400580:	b4000041 	cbz	x1, 400588 <deregister_tm_clones+0x28>
  400584:	d61f0020 	br	x1
  400588:	d65f03c0 	ret
  40058c:	d503201f 	nop

0000000000400590 <register_tm_clones>:
  400590:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400594:	9100c000 	add	x0, x0, #0x30
  400598:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40059c:	9100c021 	add	x1, x1, #0x30
  4005a0:	cb000021 	sub	x1, x1, x0
  4005a4:	9343fc21 	asr	x1, x1, #3
  4005a8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4005ac:	9341fc21 	asr	x1, x1, #1
  4005b0:	b40000a1 	cbz	x1, 4005c4 <register_tm_clones+0x34>
  4005b4:	90000002 	adrp	x2, 400000 <_init-0x480>
  4005b8:	f944f442 	ldr	x2, [x2, #2536]
  4005bc:	b4000042 	cbz	x2, 4005c4 <register_tm_clones+0x34>
  4005c0:	d61f0040 	br	x2
  4005c4:	d65f03c0 	ret

00000000004005c8 <__do_global_dtors_aux>:
  4005c8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4005cc:	910003fd 	mov	x29, sp
  4005d0:	f9000bf3 	str	x19, [sp, #16]
  4005d4:	b0000093 	adrp	x19, 411000 <__libc_start_main@GLIBC_2.17>
  4005d8:	3940c260 	ldrb	w0, [x19, #48]
  4005dc:	35000080 	cbnz	w0, 4005ec <__do_global_dtors_aux+0x24>
  4005e0:	97ffffe0 	bl	400560 <deregister_tm_clones>
  4005e4:	52800020 	mov	w0, #0x1                   	// #1
  4005e8:	3900c260 	strb	w0, [x19, #48]
  4005ec:	f9400bf3 	ldr	x19, [sp, #16]
  4005f0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4005f4:	d65f03c0 	ret

00000000004005f8 <frame_dummy>:
  4005f8:	17ffffe6 	b	400590 <register_tm_clones>

00000000004005fc <i_c_c>:
  4005fc:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400600:	910003fd 	mov	x29, sp
  400604:	52809a40 	mov	w0, #0x4d2                 	// #1234
  400608:	b9003fa0 	str	w0, [x29, #60]
  40060c:	a901ffbf 	stp	xzr, xzr, [x29, #24]
  400610:	a902ffbf 	stp	xzr, xzr, [x29, #40]
  400614:	b9003bbf 	str	wzr, [x29, #56]
  400618:	b9403fa0 	ldr	w0, [x29, #60]
  40061c:	5289ba61 	mov	w1, #0x4dd3                	// #19923
  400620:	72a20c41 	movk	w1, #0x1062, lsl #16
  400624:	9b217c01 	smull	x1, w0, w1
  400628:	d360fc21 	lsr	x1, x1, #32
  40062c:	13067c21 	asr	w1, w1, #6
  400630:	131f7c00 	asr	w0, w0, #31
  400634:	4b000020 	sub	w0, w1, w0
  400638:	b9003ba0 	str	w0, [x29, #56]
  40063c:	90000000 	adrp	x0, 400000 <_init-0x480>
  400640:	9127c000 	add	x0, x0, #0x9f0
  400644:	52801d42 	mov	w2, #0xea                  	// #234
  400648:	b9403ba1 	ldr	w1, [x29, #56]
  40064c:	97ffffa9 	bl	4004f0 <printf@plt>
  400650:	b9403ba0 	ldr	w0, [x29, #56]
  400654:	12001c00 	and	w0, w0, #0xff
  400658:	1100c000 	add	w0, w0, #0x30
  40065c:	12001c00 	and	w0, w0, #0xff
  400660:	390063a0 	strb	w0, [x29, #24]
  400664:	b9403fa0 	ldr	w0, [x29, #60]
  400668:	5290a3e1 	mov	w1, #0x851f                	// #34079
  40066c:	72aa3d61 	movk	w1, #0x51eb, lsl #16
  400670:	9b217c01 	smull	x1, w0, w1
  400674:	d360fc21 	lsr	x1, x1, #32
  400678:	13057c21 	asr	w1, w1, #5
  40067c:	131f7c00 	asr	w0, w0, #31
  400680:	4b000021 	sub	w1, w1, w0
  400684:	528ccce0 	mov	w0, #0x6667                	// #26215
  400688:	72acccc0 	movk	w0, #0x6666, lsl #16
  40068c:	9b207c20 	smull	x0, w1, w0
  400690:	d360fc00 	lsr	x0, x0, #32
  400694:	13027c02 	asr	w2, w0, #2
  400698:	131f7c20 	asr	w0, w1, #31
  40069c:	4b000042 	sub	w2, w2, w0
  4006a0:	2a0203e0 	mov	w0, w2
  4006a4:	531e7400 	lsl	w0, w0, #2
  4006a8:	0b020000 	add	w0, w0, w2
  4006ac:	531f7800 	lsl	w0, w0, #1
  4006b0:	4b000020 	sub	w0, w1, w0
  4006b4:	b9003ba0 	str	w0, [x29, #56]
  4006b8:	b9403ba0 	ldr	w0, [x29, #56]
  4006bc:	12001c00 	and	w0, w0, #0xff
  4006c0:	1100c000 	add	w0, w0, #0x30
  4006c4:	12001c00 	and	w0, w0, #0xff
  4006c8:	390067a0 	strb	w0, [x29, #25]
  4006cc:	b9403fa0 	ldr	w0, [x29, #60]
  4006d0:	528ccce1 	mov	w1, #0x6667                	// #26215
  4006d4:	72acccc1 	movk	w1, #0x6666, lsl #16
  4006d8:	9b217c01 	smull	x1, w0, w1
  4006dc:	d360fc21 	lsr	x1, x1, #32
  4006e0:	13027c21 	asr	w1, w1, #2
  4006e4:	131f7c00 	asr	w0, w0, #31
  4006e8:	4b000021 	sub	w1, w1, w0
  4006ec:	528ccce0 	mov	w0, #0x6667                	// #26215
  4006f0:	72acccc0 	movk	w0, #0x6666, lsl #16
  4006f4:	9b207c20 	smull	x0, w1, w0
  4006f8:	d360fc00 	lsr	x0, x0, #32
  4006fc:	13027c02 	asr	w2, w0, #2
  400700:	131f7c20 	asr	w0, w1, #31
  400704:	4b000042 	sub	w2, w2, w0
  400708:	2a0203e0 	mov	w0, w2
  40070c:	531e7400 	lsl	w0, w0, #2
  400710:	0b020000 	add	w0, w0, w2
  400714:	531f7800 	lsl	w0, w0, #1
  400718:	4b000020 	sub	w0, w1, w0
  40071c:	b9003ba0 	str	w0, [x29, #56]
  400720:	b9403ba0 	ldr	w0, [x29, #56]
  400724:	12001c00 	and	w0, w0, #0xff
  400728:	1100c000 	add	w0, w0, #0x30
  40072c:	12001c00 	and	w0, w0, #0xff
  400730:	39006ba0 	strb	w0, [x29, #26]
  400734:	b9403fa1 	ldr	w1, [x29, #60]
  400738:	528ccce0 	mov	w0, #0x6667                	// #26215
  40073c:	72acccc0 	movk	w0, #0x6666, lsl #16
  400740:	9b207c20 	smull	x0, w1, w0
  400744:	d360fc00 	lsr	x0, x0, #32
  400748:	13027c02 	asr	w2, w0, #2
  40074c:	131f7c20 	asr	w0, w1, #31
  400750:	4b000042 	sub	w2, w2, w0
  400754:	2a0203e0 	mov	w0, w2
  400758:	531e7400 	lsl	w0, w0, #2
  40075c:	0b020000 	add	w0, w0, w2
  400760:	531f7800 	lsl	w0, w0, #1
  400764:	4b000020 	sub	w0, w1, w0
  400768:	b9003ba0 	str	w0, [x29, #56]
  40076c:	b9403ba0 	ldr	w0, [x29, #56]
  400770:	12001c00 	and	w0, w0, #0xff
  400774:	1100c000 	add	w0, w0, #0x30
  400778:	12001c00 	and	w0, w0, #0xff
  40077c:	39006fa0 	strb	w0, [x29, #27]
  400780:	910063a1 	add	x1, x29, #0x18
  400784:	90000000 	adrp	x0, 400000 <_init-0x480>
  400788:	91280000 	add	x0, x0, #0xa00
  40078c:	97ffff59 	bl	4004f0 <printf@plt>
  400790:	d503201f 	nop
  400794:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400798:	d65f03c0 	ret

000000000040079c <h_c_c>:
  40079c:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  4007a0:	910003fd 	mov	x29, sp
  4007a4:	5299bde0 	mov	w0, #0xcdef                	// #52719
  4007a8:	72a01560 	movk	w0, #0xab, lsl #16
  4007ac:	b9003fa0 	str	w0, [x29, #60]
  4007b0:	a901ffbf 	stp	xzr, xzr, [x29, #24]
  4007b4:	a902ffbf 	stp	xzr, xzr, [x29, #40]
  4007b8:	b9003bbf 	str	wzr, [x29, #56]
  4007bc:	b9403fa0 	ldr	w0, [x29, #60]
  4007c0:	13147c00 	asr	w0, w0, #20
  4007c4:	b9003ba0 	str	w0, [x29, #56]
  4007c8:	b9403ba0 	ldr	w0, [x29, #56]
  4007cc:	12001c00 	and	w0, w0, #0xff
  4007d0:	11015c00 	add	w0, w0, #0x57
  4007d4:	12001c00 	and	w0, w0, #0xff
  4007d8:	390063a0 	strb	w0, [x29, #24]
  4007dc:	b9403fa0 	ldr	w0, [x29, #60]
  4007e0:	13107c00 	asr	w0, w0, #16
  4007e4:	b9003ba0 	str	w0, [x29, #56]
  4007e8:	b9403ba0 	ldr	w0, [x29, #56]
  4007ec:	12000c00 	and	w0, w0, #0xf
  4007f0:	b9003ba0 	str	w0, [x29, #56]
  4007f4:	b9403ba0 	ldr	w0, [x29, #56]
  4007f8:	12001c00 	and	w0, w0, #0xff
  4007fc:	11015c00 	add	w0, w0, #0x57
  400800:	12001c00 	and	w0, w0, #0xff
  400804:	390067a0 	strb	w0, [x29, #25]
  400808:	b9403fa0 	ldr	w0, [x29, #60]
  40080c:	130c7c00 	asr	w0, w0, #12
  400810:	b9003ba0 	str	w0, [x29, #56]
  400814:	b9403ba0 	ldr	w0, [x29, #56]
  400818:	12000c00 	and	w0, w0, #0xf
  40081c:	b9003ba0 	str	w0, [x29, #56]
  400820:	b9403ba0 	ldr	w0, [x29, #56]
  400824:	12001c00 	and	w0, w0, #0xff
  400828:	11015c00 	add	w0, w0, #0x57
  40082c:	12001c00 	and	w0, w0, #0xff
  400830:	39006ba0 	strb	w0, [x29, #26]
  400834:	b9403fa0 	ldr	w0, [x29, #60]
  400838:	13087c00 	asr	w0, w0, #8
  40083c:	b9003ba0 	str	w0, [x29, #56]
  400840:	b9403ba0 	ldr	w0, [x29, #56]
  400844:	12000c00 	and	w0, w0, #0xf
  400848:	b9003ba0 	str	w0, [x29, #56]
  40084c:	b9403ba0 	ldr	w0, [x29, #56]
  400850:	12001c00 	and	w0, w0, #0xff
  400854:	11015c00 	add	w0, w0, #0x57
  400858:	12001c00 	and	w0, w0, #0xff
  40085c:	39006fa0 	strb	w0, [x29, #27]
  400860:	b9403fa0 	ldr	w0, [x29, #60]
  400864:	13047c00 	asr	w0, w0, #4
  400868:	b9003ba0 	str	w0, [x29, #56]
  40086c:	b9403ba0 	ldr	w0, [x29, #56]
  400870:	12000c00 	and	w0, w0, #0xf
  400874:	b9003ba0 	str	w0, [x29, #56]
  400878:	b9403ba0 	ldr	w0, [x29, #56]
  40087c:	12001c00 	and	w0, w0, #0xff
  400880:	11015c00 	add	w0, w0, #0x57
  400884:	12001c00 	and	w0, w0, #0xff
  400888:	390073a0 	strb	w0, [x29, #28]
  40088c:	b9403fa0 	ldr	w0, [x29, #60]
  400890:	b9003ba0 	str	w0, [x29, #56]
  400894:	b9403ba0 	ldr	w0, [x29, #56]
  400898:	12000c00 	and	w0, w0, #0xf
  40089c:	b9003ba0 	str	w0, [x29, #56]
  4008a0:	b9403ba0 	ldr	w0, [x29, #56]
  4008a4:	12001c00 	and	w0, w0, #0xff
  4008a8:	11015c00 	add	w0, w0, #0x57
  4008ac:	12001c00 	and	w0, w0, #0xff
  4008b0:	390077a0 	strb	w0, [x29, #29]
  4008b4:	910063a1 	add	x1, x29, #0x18
  4008b8:	90000000 	adrp	x0, 400000 <_init-0x480>
  4008bc:	91286000 	add	x0, x0, #0xa18
  4008c0:	97ffff0c 	bl	4004f0 <printf@plt>
  4008c4:	d503201f 	nop
  4008c8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  4008cc:	d65f03c0 	ret

00000000004008d0 <main>:
  4008d0:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4008d4:	910003fd 	mov	x29, sp
  4008d8:	52800600 	mov	w0, #0x30                  	// #48
  4008dc:	39007fa0 	strb	w0, [x29, #31]
  4008e0:	39407fa1 	ldrb	w1, [x29, #31]
  4008e4:	39407fa2 	ldrb	w2, [x29, #31]
  4008e8:	90000000 	adrp	x0, 400000 <_init-0x480>
  4008ec:	9128c000 	add	x0, x0, #0xa30
  4008f0:	97ffff00 	bl	4004f0 <printf@plt>
  4008f4:	52800020 	mov	w0, #0x1                   	// #1
  4008f8:	39007fa0 	strb	w0, [x29, #31]
  4008fc:	39407fa1 	ldrb	w1, [x29, #31]
  400900:	39407fa2 	ldrb	w2, [x29, #31]
  400904:	90000000 	adrp	x0, 400000 <_init-0x480>
  400908:	9128c000 	add	x0, x0, #0xa30
  40090c:	97fffef9 	bl	4004f0 <printf@plt>
  400910:	52800620 	mov	w0, #0x31                  	// #49
  400914:	39007fa0 	strb	w0, [x29, #31]
  400918:	39407fa1 	ldrb	w1, [x29, #31]
  40091c:	39407fa2 	ldrb	w2, [x29, #31]
  400920:	90000000 	adrp	x0, 400000 <_init-0x480>
  400924:	9128c000 	add	x0, x0, #0xa30
  400928:	97fffef2 	bl	4004f0 <printf@plt>
  40092c:	97ffff34 	bl	4005fc <i_c_c>
  400930:	97ffff9b 	bl	40079c <h_c_c>
  400934:	d503201f 	nop
  400938:	a8c27bfd 	ldp	x29, x30, [sp], #32
  40093c:	d65f03c0 	ret

0000000000400940 <__libc_csu_init>:
  400940:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400944:	910003fd 	mov	x29, sp
  400948:	a901d7f4 	stp	x20, x21, [sp, #24]
  40094c:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf5c0>
  400950:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf5c0>
  400954:	91374294 	add	x20, x20, #0xdd0
  400958:	913722b5 	add	x21, x21, #0xdc8
  40095c:	a902dff6 	stp	x22, x23, [sp, #40]
  400960:	cb150294 	sub	x20, x20, x21
  400964:	f9001ff8 	str	x24, [sp, #56]
  400968:	2a0003f6 	mov	w22, w0
  40096c:	aa0103f7 	mov	x23, x1
  400970:	9343fe94 	asr	x20, x20, #3
  400974:	aa0203f8 	mov	x24, x2
  400978:	97fffec2 	bl	400480 <_init>
  40097c:	b4000194 	cbz	x20, 4009ac <__libc_csu_init+0x6c>
  400980:	f9000bb3 	str	x19, [x29, #16]
  400984:	d2800013 	mov	x19, #0x0                   	// #0
  400988:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  40098c:	aa1803e2 	mov	x2, x24
  400990:	aa1703e1 	mov	x1, x23
  400994:	2a1603e0 	mov	w0, w22
  400998:	91000673 	add	x19, x19, #0x1
  40099c:	d63f0060 	blr	x3
  4009a0:	eb13029f 	cmp	x20, x19
  4009a4:	54ffff21 	b.ne	400988 <__libc_csu_init+0x48>  // b.any
  4009a8:	f9400bb3 	ldr	x19, [x29, #16]
  4009ac:	a941d7f4 	ldp	x20, x21, [sp, #24]
  4009b0:	a942dff6 	ldp	x22, x23, [sp, #40]
  4009b4:	f9401ff8 	ldr	x24, [sp, #56]
  4009b8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  4009bc:	d65f03c0 	ret

00000000004009c0 <__libc_csu_fini>:
  4009c0:	d65f03c0 	ret

Disassembly of section .fini:

00000000004009c4 <_fini>:
  4009c4:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4009c8:	910003fd 	mov	x29, sp
  4009cc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4009d0:	d65f03c0 	ret
